The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller.
A continuous challenge to the disc drive industry is to continually reduce cost per megabyte while increasing performance and capacity. As consumer demand for low cost/high capacity/high performance non-volatile storage grows, the pressure to create new and innovative solutions is tremendous. One area of great focus is electronics cost and performance. One way to trade off costs versus performance is to design a buffer manager that can support a range of different speed RAMs so that a given set of electronics can be as inexpensive as possible for the required performance. Thus it is important to maximize the efficiency of the RAM by creating buffer cycles that are as close as possible to the RAM speed. Because of pad and board trace delays that vary with the environment some overhead must be designed into the buffer cycle. Thus, a serious need exists for a clocking scheme for the buffer manager that allows various speed RAMs to be easily supported with a constant overhead.
A typical generation of electronics in a state of the art disc drive today supports multiple speeds of RAMs by supplying different clock frequencies with different RAM speeds, and using one or two clocks per buffer cycle. This results in a complex design with varying overheads for the various speed RAMs. FIG. 9 illustrates the problem created by such a complex design.
The field of which the present invention is used can best be understood by reviewing FIGS. 1, 2 and 3. FIG. 1 shows a disc drive of the type in which this invention would be used connected to a host computer 12 via a host interface 14. The hard disc drive 10 contains drive electronics 16, the hard disc 18 on which data is stored, and the mechanical components 20 which control the rotation of the hard disc and the positioning of the read/write arm.
FIG. 2 shows the drive electronics which are generally present in current state of the art disc drives. The drive electronics 16 include, among other things, a microcontroller 20; a hard disc controller 22; a buffer RAM 26; and servo electronics 24. The microcontroller 20 controls all aspects of the drive operation at a high level. The microcontroller 20 communicates through the interface 14 with the host computer 12, and generally sequences operation of the drive and electronics to read from and write to the hard disc 18. The servo electronics 24 generate control signals for the mechanical components of the disc drive to ensure the transducer is properly aligned with a desired store location in the disc drive. The buffer RAM 26 is the buffer memory in the system. It is used for temporary storage of data which is being transferred between the host computer 12 and the hard disc drive 10. Finally, the hard disc controller 22 is a low level controller for the disc drive. Under commands from the microcontroller 20, it generates control signal for the various components of the disc drive to control the transfer of data; to generate and check error correction codes; to store status information and other data used by the microcontroller 20; and to format and synchronize communications signals from various parts of the disc drive and host computer.
FIG. 3 shows details of the hard disc controller 22 and includes, among other things, a host interface 14; a microcontroller interface 32; a disc interface 34; an ECC checker/generator 36; a clock generator 38; and a buffer controller 39.
The host interface 14 is for receiving commands from the host computer 12; the commands herein are formatted in order to be read by the microcontroller 20. The microcontroller interface 32 is for communicating with the microcontroller. Through this interface, the microcontroller reads information registers housed in the hard disc controller and directs the operation of the hard disc 18. The disc interface 34 is for communicating with the read/write heads on the disc. Data comes through this interface and is formatted for use by other components. The clock generator 38 generates several clock signals used by the hard disc drive components. The ECC generator/checker 36 generates error control and correction information for data which is being transferred to/from the disc drive. It also checks ECC information coming off the drive for accuracy. Finally, the buffer controller controls access to the RAM buffer 26 and is the focus of the present invention. When data is read from the drive, it is first formatted and then stored in the buffer. The RAM buffer acts as a synchronization area for data, and allows data coming off the disc in one format at one speed to be transmitted to the microcontroller 20, the ECC 36, or the host computer 12 at another speed or format. Similar functions are accomplished in reverse for data being written. Many components may need to read/write from/to the RAM buffer. The ECC generator/checker will read/write data from/to the RAM buffer to correct errors in the data read from the disc. The disc interface will need access to the RAM buffer to store data from the disc or to read data that is to go to the disc. The microcontroller can also access the RAM buffer directly to monitor/modify data. The host computer accesses the buffer to store data in route to the disc or to receive data from the disc. It is the job of the buffer controller to synchronize these commands and provide access in a timely and efficient manner to the buffer memory.
It is an object of the present invention to provide a buffer manager that easily synchronizes all requests from various sources, and utilizes a single clock cycle of varying periods to accommodate all speeds of RAMs. Buffer managers need to manage access to different speeds of RAM, because RAMs of different speeds may be available on the market at different costs at different times. It is important to easily and reliably be able to use whatever RAM is available in a disc drive controller without having to provide a complex buffer manager. It is a further objective of this invention to provide direct gating of control signals of the RAM, so that complexity of the buffer manager is simplified.
In current electronic buffer manager designs, the buffer manager requires multiple base synthesizer frequencies to generate the base clock. It is an objective of the present invention to require just one base synthesizer frequency in order to reduce the cost and maximize simplicity of the buffer manager design.
In current electronic designs for the buffer manager, the manager requires state machines that use variable numbers of clocks to generate buffer cycles. Therefore, it is an object of this invention to use one clock cycle per buffer cycle, thus simplifying the design and reducing associated costs.
A further objective of the invention better utilizes available memory bandwidth, thereby allowing cheaper memories to be used for a given level of performance.
These and other objectives of the invention are achieved by providing a state machine in the buffer manager which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic.
Other features and advantages of the present invention would become apparent to a person of skill in the art who studies the present invention disclosure. Therefore, a more detailed description of a preferred embodiment of the invention is given with respect to the following drawings.